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ISL59452
Data Sheet September 24, 2007 FN6254.0
Triple 4:1 Single Supply Video Multiplexing Amplifier
The ISL59452 is a 4-input, single-supply, triple video multiplexer suited for component video applications. The device features single +5V supply operation, high bandwidth and TTL/CMOS logic compatible gain select (AV2) of x1 or x2. When HIZ is pulled high, the outputs are put into highimpedance states and the video inputs are disconnected putting the device in a low power state. This is an essential feature for power sensitive applications. The ISL59452 also features fast channel switching at pixel rates to allow for video overlays. The ISL59452 will drive 150 loads making it suitable for 75 cable driving applications. The ISL59452 is ideal for RGB, YPbPr, as well as S-Video and composite applications. The ISL59452 comes in a 32 Ld QFN package and is specified for operation over -40C to +85C temperature range.
Features
* 250MHz Small Signal Bandwidth (GAIN 1) * Capable of Pixel Rate Channel Switching * +5V Single Supply Operation * TTL/CMOS Compatible Gain Select of x1 or x2 * High Impedance Output Setting * Ideal for RGB/YPbPr/S-Video/Composite Video Signals * 150 Output Load Capability for Video Cable Driving * 0.0013% Differential Gain and 0.035 Differential Phase Accuracy * Pb-Free (RoHS Compliant)
Applications
* SDTVs and HDTVs * Set-Top Boxes * Video Overlay * Security Video
Ordering Information
PART NUMBER (Note) ISL59452IRZ ISL59452IRZ-T7* PART MARKING PACKAGE (Pb-Free) PKG. DWG. # L32.5x5 L32.5x5
* Broadcast Video Equipment
ISL594 52IRZ 32 Ld 5x5 QFN ISL594 52IRZ 32 Ld 5x5 QFN
Pinout
ISL59452 (32 LD QFN) TOP VIEW
32 GND 27 GND 25 AV2 24 ROUT 23 GND
2/1
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
31 G0 30 B0
R1 1 B1 2 G1 3 GND 4 V+ 5
2/1
26 HIZ
28 V+
29 R0
22 GND 21 BOUT 20 V+
2/1
GND 6 R2 7 B2 8 GND 10 R3 11 B3 12 G3 13 G2 9 Gray = Thermal Pad S1 14 S0 15 GND 16
19 V+ 18 GOUT 17 GND
EXPOSED THERMAL PAD MUST BE CONNECTED TO GND.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL59452
Absolute Maximum Ratings (TA = +25C)
Supply Voltage (V+ to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Input Voltage to GND . . . . . . . . . . . . . . . . . GND - 0.5V to V+ + 0.5V Voltage between HIZ, AV2 and GND . . . . . . . . . GND -0.5;V+ +0.5V Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/s Digital and Analog Input Current (Note 1) . . . . . . . . . . . . . . . . 50mA Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7). . . .2500V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Thermal Information
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . .-40C to +125C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values. 2. Parts are 100% tested at +25C. Over temperature limits established by characterization and are not production tested.
Electrical Specifications
V+ = +5V, GND = 0V, TA = +25C, RL = 150 to GND, AV2 = HIZ = 0.8V, unless otherwise specified. CONDITIONS MIN (Note 2) TYP MAX (Note 2) UNIT
PARAMETER DC CHARACTERISTICS V+ +IS Enabled +IS Disabled VOS
DESCRIPTION
Supply Voltage Enabled Supply Current Disabled Supply Current Output Offset Voltage No load, VIN = 0V, HIZ = 0.8V No load, VIN = 0V, HIZ = 2.0V AV2 = 0.8V, GAIN = 1, VIN = 0.1V AV2 = 2.0V, GAIN = 2, VIN = 0.1V
4.5
5.0 45 3
5.5 75 5 35 35 -2 2.5 1.02 2.05
V mA mA mV mV A k V/V V/V dB
-35 -35 -6 1.5 .98 1.95 50
0 0 -4 2 1 1.99 55
IB ROUT-DIS AV
Input Bias Current Disabled Output Resistance (DC) Voltage Gain
VIN = 2.2V, No Load HIZ = 2.0V AV2 = 0.8V, GAIN = 1 AV2 = 2.0V, GAIN = 2
PSRRDC
Power Supply Rejection Ratio
V+ = 4.5V to 5.5V
OUTPUT AMPLIFIERS VOUT+ VOUTISC Output High Swing Output Low Swing Short Circuit Current RL = 150, VIN = 4V, AV2 = 2.0V, GAIN = 2 RL = 150,VIN = 0V, AV2 = 2.0V, GAIN = 2 Sourcing, VIN = 3V, AV2 = 2.0V, RL = 10 to GND, GAIN = 2 Sinking, VIN = 0V, RL = 10 to +3V LOGIC (AV2, HIZ, S1, S0) VIH VIL IIH Input High Voltage (HIGH) Input Low Voltage (LOW) Input High Current (Logic Inputs) S1 = S0 = 5V (no pull-up or pull-down) AV2 = HIZ= 5V (300k internal pull-downs) IIL Input Low Current (Logic Inputs) S1 = S0 = 0V (no pull-up or pull-down) AV2 = HIZ = 5V (300k internal pull-downs) AC GENERAL PSRR XTALK Power Supply Rejection Ratio Channel to Channel Crosstalk (ROUT/BOUT to Green Input) VIN = 0V, f = 10kHz to 10MHz, V+ = 5VDC +100mVP-P sine wave f = 10MHz, VIN = 0.7VP-P; (GAIN = 1) f = 10MHz, VIN = 0.7VP-P; (GAIN = 2) 55 75 70 dB dB dB -2 8 -2 -2 0 17 0 0 2 0.8 2 34 2 2 V V A A A A 125 57 3.5 30 V mV mA mA
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FN6254.0 September 24, 2007
ISL59452
Electrical Specifications
V+ = +5V, GND = 0V, TA = +25C, RL = 150 to GND, AV2 = HIZ = 0.8V, unless otherwise specified. (Continued) CONDITIONS MIN (Note 2) TYP 90 90 0.0013 0.035 250 210 240 200 40 33 480 980 300 568 MAX (Note 2) UNIT dB dB % MHz MHz MHz MHz MHz MHz V/s V/s V/s V/s
PARAMETER Off - ISO
DESCRIPTION
Off-State Isolation (any de-selected output f = 10MHz, Ch-Ch Off Isolation to driven input) VIN = 0.7VP-P; (GAIN = 1) f = 10MHz, Ch-Ch Off Isolation VIN = 0.7VP-P; (GAIN = 2)
dG dP BW
Differential Gain Error Differential Phase Error Small Signal -3dB Bandwidth
RL = 150 RL = 150 VOUT = 0.1VP-P; RL = 150, CL = 0.6pF (GAIN = 1) VOUT = 0.2VP-P; RL = 150, CL = 0.6pF (GAIN = 2)
Large Signal -3dB Bandwidth
VOUT = 0.7VP-P; RL = 150, CL = 0.6pF (GAIN = 1) VOUT = 1.4VP-P; RL = 150, CL = 0.6pF (GAIN = 2)
BW_0.1
0.1dB Bandwidth
VOUT = 1.4VP-P; RL = 150, CL = 0.6pF (GAIN = 1) VOUT = 1.4VP-P; RL = 150, CL = 0.6pF (GAIN = 2)
SR+
Positive Slew Rate
VIN = 0.5V to 2.5V, time = 20% to 80%, RL = 150, AV2 = 0.8V, CL = 2.1pF, GAIN = 1 VIN = 0.5V to 1.5V, time = 20% to 80%, RL = 150, AV2 = 2.0V, CL = 2.1pF, GAIN = 2
SR-
Negative Slew Rate
VIN = 2.5V to 0.5V, time = 80% to 20%, RL = 150, AV2 = 0.8V, CL = 2.1pF, GAIN = 1 VIN = 1.5V to 0.5V, time = 80% to 20%, RL = 150, AV2 = 2.0V, CL = 2.1pF, GAIN = 2
TRANSIENT RESPONSE tR Rise Time 10% to 90% VOUT = 1VP-P; RL = 150, CL = 2.1pF, AV2 = 0.8V, GAIN = 1 VOUT = 1VP-P; RL = 150, CL = 2.1pF, AV2 = 2.0V, GAIN = 2 VOUT = 2VP-P; RL = 150, CL = 2.1pF, AV2 = 2.0V, GAIN = 2 tF Fall Time 90% to 10% VOUT = 1VP-P; RL = 150, CL = 2.1pF, AV2 = 0.8V, GAIN = 1 VOUT = 1VP-P; RL = 150, CL = 2.1pF, AV2 = 2.0V, GAIN = 2 VOUT = 2VP-P; RL = 150, CL = 2.1pF, AV2 = 2.0V, GAIN = 2 tS 1% Settling Time to 1% VOUT = 1VP-P; RL = 150, CL = 2.1pF, GAIN = 1, time from 90% crossing to 1% of final value VOUT = 1VP-P; RL = 150, CL = 2.1pF, GAIN = 2, time from 90% crossing to 1% of final value SWITCHING CHARACTERISTICS VGLITCH HIZ High to Low Switching Glitch VIN = 1V, RL = 150; CL = 2.1pF, AV2 = 0.8V VIN = 1V, RL = 150; CL = 2.1pF, AV2 = 2.0V 400 300 mVP-P mVP-P 1.72 1 1.88 2.7 2.2 2.7 3 ns ns ns ns ns ns
5
ns
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FN6254.0 September 24, 2007
ISL59452
Electrical Specifications
V+ = +5V, GND = 0V, TA = +25C, RL = 150 to GND, AV2 = HIZ = 0.8V, unless otherwise specified. (Continued) CONDITIONS 1.2V logic threshold to 10% movement of analog output 1.2V logic threshold to 10% movement of analog output 1.2V logic threshold to 10% movement of analog output 1.2V logic threshold to 10% movement of analog output 10% input to 10% output, VIN = 100mVP-P 10% input to 10% output, VIN = 700mVP-P MIN (Note 2) TYP 3 5 30 220 5 2 MAX (Note 2) UNIT ns ns ns ns ns ns
PARAMETER tSW-L-H tSW-H-L tHIZ-L-H tHIZ-H-L tpd
DESCRIPTION Channel Switching Delay Time Low to High Channel Switching Delay Time High to Low HIZ Switching Delay Time Low to High HIZ Switching Delay Time High to Low Propagation Delay
Settling Time Diagram
1% OF FINAL VALUE BAND 1% OF FINAL
VALUE BAND
FINAL VALUE FINAL VALUE 90% OF FINAL VALUE 90% FINAL VALUE
10% FINAL VALUE 10%OF FINAL VALUE
tR
ts 1% tS 1%
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FN6254.0 September 24, 2007
ISL59452 Typical Application Diagram
+5V
1nF C
10nF
1F
RED/Pr R0 75 GREEN/Y G0 75 BLUE/Pb B0 75 RED/Pr R1 75 GREEN/Y G1 75 BLUE/Pb B1 75 RED/Pr R2 75 GREEN/Y G2 75 BLUE/Pb B2 75 RED/Pr R3 75 GREEN/Y 75 BLUE/Pb 75 B3 G3 3 3 3
S1
S0
AV2
V+
X1/ X2
75 ROUT VIDEO OUT
RED/Pr
00 01 10 11 X1/ X2 75 GOUT GREEN/Y
VIDEO OUT
3 S1, S0 X1/ X2 BOUT 75 BLUE/Pb
VIDEO OUT
ISL59452
HIZ GND
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FN6254.0 September 24, 2007
ISL59452 Typical Performance Curves
5 NORMALIZED MAGNITUDE (dB) VIN = 100mVP-P 0 -5 CL = 0.6pF -10 -15 -20 -25 100k CL = 5.3pF CL = 3.3pF NORMALIZED MAGNITUDE (dB) CL = 12.6pF CL = 7.4pF CL = 8.8pF
V+ = +5V, RL = 150 to GND, CL = 0.6pF, TA = +25C, unless otherwise specified.
5 VIN = 700mVP-P 0 -5 -10 -15 -20 -25 100k CL = 0.6pF CL = 12.6pF CL = 7.4pF CL = 8.8pF CL = 3.3pF CL = 2.1pF CL = 5.3pF 1M 10M 100M 1G 10G
1M
10M
100M
1G
10G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. SMALL SIGNAL GAIN vs FREQUENCY vs CL INTO 150 LOAD, GAIN = 1
FIGURE 2. LARGE SIGNAL GAIN vs FREQUENCY vs CL INTO 150 LOAD, GAIN = 1
NORMALIZED MAGNITUDE (dB)
VIN = 100mVP-P 0 -5 -10 -15 -20 -25 100k CL = 7.4pF CL = 2.1pF
NORMALIZED MAGNITUDE (dB)
5 CL = 12.6pF CL = 8.8pF CL = 5.3pF CL = 3.3pF
5 VIN = 700mVP-P 0 -5 -10 -15 -20 CL = 5.3pF -25 100k 1M 10M 100M 1G 10G CL =0.6pF CL = 12.6pF CL = 8.8pF CL = 2.1pF CL = 7.4pF
CL = 0.6pF
1M
10M
100M
1G
10G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 3. SMALL SIGNAL GAIN vs FREQUENCY vs CL INTO 150 LOAD, GAIN = 2
FIGURE 4. LARGE SIGNAL GAIN vs FREQUENCY vs CL INTO 150 LOAD, GAIN = 2
NORMALIZED MAGNITUDE (dB)
NORMALIZED MAGNITUDE (dB)
1 VIN = 100mVP-P 0 CL = 7.4pF -1 -2 -3 CL = 0.6pF -4 -5 100k CL = 3.3pF 1M 10M FREQUENCY (Hz) 100M 1G CL = 12.6pF
1 VIN = 700mVP-P 0 -1 -2 -3
CL = 12.6pF CL = 7.4pF
CL = 0.6pF -4 CL = 3.3pF -5 100k 1M 10M FREQUENCY (Hz) 100M 1G
FIGURE 5. SMALL SIGNAL GAIN FLATNESS, GAIN = 1
FIGURE 6. LARGE SIGNAL GAIN FLATNESS, GAIN = 1
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FN6254.0 September 24, 2007
ISL59452 Typical Performance Curves
NORMALIZED MAGNITUDE (dB) 1 VIN = 100mVP-P 0 -1 -2 -3 -4 -5 100k 1M 10M FREQUENCY (Hz) 100M 1G CL = 0.6pF CL = 3.3pF CL = 7.4pF
V+ = +5V, RL = 150 to GND, CL = 0.6pF, TA = +25C, unless otherwise specified. (Continued)
NORMALIZED MAGNITUDE (dB) 1 VIN = 700mVP-P 0 -1 -2 -3 -4 CL = 3.3pF -5 100k 1M 10M FREQUENCY (Hz) 100M 1G CL = 0.6pF CL = 7.4pF
FIGURE 7. SMALL SIGNAL GAIN FLATNESS, GAIN = 2
FIGURE 8. LARGE SIGNAL GAIN FLATNESS, GAIN = 2
30.6 30.4 30.2 30.0 29.8 29.6 29.4 4.5 DISABLED CURRENT (mA) NO INPUT NO LOAD
2.85 2.80 2.75 2.70 2.65 2.60 2.55 2.50 2.45 2.40 2.35 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 2.30 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 HIZ = HIGH
SUPPLY CURRENT (mA)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FIGURE 9. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 10. DISABLED SUPPLY CURRENT vs SUPPLY VOLTAGE
14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 10k 100k 1M FREQUENCY (Hz) 10M 100M GAIN = 1 IMPEDANCE (k) IMPEDANCE () GAIN = 2
1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 0.3 0.1 10k 100k 1M FREQUENCY (Hz) 10M
HIZ = HIGH
100M
FIGURE 11. ZOUT vs FREQUENCY - ENABLED
FIGURE 12. ZOUT vs FREQUENCY - DISABLED
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FN6254.0 September 24, 2007
ISL59452 Typical Performance Curves
1000
V+ = +5V, RL = 150 to GND, CL = 0.6pF, TA = +25C, unless otherwise specified. (Continued)
0 VAC = 100mVP-P -10
IMPEDANCE (k)
100 PSRR (dB) -20 -30 -40 -50 0.1 10k -60 100k
10
1
100k
1M FREQUENCY (Hz)
10M
100M
1M
10M
100M
FREQUENCY (Hz)
FIGURE 13. ZIN vs FREQUENCY
FIGURE 14. PSRR vs FREQUENCY
0 -10 CROSSTALK (dB) -20 -30 -40 -50 -60 -70 -80 -90 100k 1M 10M 100M 1G 10G GREEN TO RED GAIN = 2 GREEN TO RED GAIN = 1 GREEN TO BLUE GAIN = 1 GREEN INPUT DRIVEN 100mVP-P TO ROUT/GOUT TO GREEN TO BLUE GAIN = 2 CROSSTALK (dB)
0 1 INPUT DRIVEN TO 100mVP-P TO -10 ANY DE-SELECTED OUTPUT -20 -30 -40 -50 -60 -70 -80 -90 -100 100k 1M 10M 100M 1G 10G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 15. CROSSTALK
FIGURE 16. OFF ISOLATION
0 -10 -20 CROSSTALK (dB) -30 nV/Hz 1M 10M 100M 1G 10G -40 -50 -60 -70 -80 -90 -100 100k HIZ = HIGH 1 INPUT DRIVEN TO 100mVP-P TO ANY OUTPUT
900 800 700 600 500 400 300 200 100 0 10 100 1k FREQUENCY (Hz) 10k 100k
FREQUENCY (Hz)
FIGURE 17. DISABLED ISOLATION
FIGURE 18. OUTPUT REFERRED NOISE vs FREQUENCY
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FN6254.0 September 24, 2007
ISL59452 Typical Performance Curves
0.0020 DIFFERENTIAL PHASE () DIFFERENTIAL GAIN (%) 0.0015 0.0010 0.0005 GAIN = 1 0.0000 -0.0005 -0.0010 0.3 GAIN = 2 VIN = 100mVP-P f = 3.58MHz
V+ = +5V, RL = 150 to GND, CL = 0.6pF, TA = +25C, unless otherwise specified. (Continued)
0.02 GAIN = 1 0.01 0.00 -0.01 -0.02 -0.03 -0.04 -0.05 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 GAIN = 2 VIN = 100mVP-P f = 3.58MHz
0.4
0.5
0.6
0.7
0.8
0.9
1.0
DC INPUT VOLTAGE (V)
DC INPUT VOLTAGE (V)
FIGURE 19. DIFFERENTIAL GAIN; fO = 3.58MHz, RL = 150
FIGURE 20. DIFFERENTIAL PHASE; fO = 3.58MHz, RL = 150
INPUT
INPUT = CH1 OUTPUT = CH2 CH1 = 50mV/DIV CH2 = 50mV/DIV TIMEBASE = 10ns/DIV
INPUT
INPUT = CH1 OUTPUT = CH2 CH1 = 50mV/DIV CH2 = 100mV/DIV TIMEBASE = 10ns/DIV
OUTPUT
OUTPUT
FIGURE 21. SMALL SIGNAL TRANSIENT RESPONSE; GAIN = 1
FIGURE 22. SMALL SIGNAL TRANSIENT RESPONSE; GAIN = 2
INPUT
INPUT = CH1 OUTPUT = CH2 CH1 = 500mV/DIV CH2 = 500mV/DIV TIMEBASE = 10ns/DIV
INPUT
INPUT = CH1 OUTPUT = CH2 CH1 = 500mV/DIV CH2 = 1.0V/DIV TIMEBASE = 10ns/DIV
OUTPUT
OUTPUT
FIGURE 23. LARGE SIGNAL TRANSIENT RESPONSE; GAIN = 1
FIGURE 24. LARGE SIGNAL TRANSIENT RESPONSE; GAIN = 2
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FN6254.0 September 24, 2007
ISL59452 Typical Performance Curves
V+ = +5V, RL = 150 to GND, CL = 0.6pF, TA = +25C, unless otherwise specified. (Continued)
HIZ HIZ HIZ = CH1 OUTPUT = CH2 CH1 = 1V/DIV CH2 = 100mV/DIV TIMEBASE = 100ns/DIV HIZ = CH1 OUTPUT = CH2 CH1 = 1V/DIV CH2 = 100mV/DIV TIMEBASE = 100ns/DIV
OUTPUT
OUTPUT
FIGURE 25. HIZ SWITCHING GLITCH, VIN = 0, GAIN = 1
FIGURE 26. HIZ SWITCHING GLITCH, VIN = 0, GAIN = 2
HIZ HIZ HIZ = CH1 OUTPUT = CH2 CH1 = 1V/DIV CH2 = 500mV/DIV TIMEBASE = 100ns/DIV OUTPUT S1, S0 = CH1 OUTPUT = CH2 CH1 =1V/DIV CH2 = 500mV/DIV TIMEBASE = 100ns/DIV OUTPUT
tHIZ-L-H
tHIZ-H-L
FIGURE 27. HIZ TIMING, GAIN = 1
FIGURE 28. HIZ TIMING, GAIN = 2
tSW-L-H
S1, S0 = CH1 OUTPUT = CH2 CH1 =1V/DIV CH2 = 500mV/DIV TIMEBASE = 5ns/DIV
tSW-H-L
FIGURE 29. CHANNEL TO CHANNEL SWITCHING TIME
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FN6254.0 September 24, 2007
ISL59452 Typical Performance Curves
V+ = +5V, RL = 150 to GND, CL = 0.6pF, TA = +25C, unless otherwise specified. (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 3.0 2.857W POWER DISSIPATION (W) POWER DISSIPATION (W) 1.0 0.8 758mW 0.6 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) QFN32 JA = 125C/W 2.5 2.0 1.5 1.0 0.5 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) QFN32 JA = 35C/W
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.2
FIGURE 30. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 31. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Functional Block Diagram (Each Output Channel)
AV2 S0 S1 R0/G0/B0 R1/G1B/1 R2/G2/B2 R3/G3/B3 x2/1 V+ ROUT GOUT BOUT GND
TABLE 1. CHANNEL SELECT LOGIC TABLE S1 0 0 1 1 X S0 0 1 0 1 X HIZ 0 0 0 0 1 OUTPUT R0, G0, B0 R1, G1, B1 R2, G2, B2 R3, G3, B3 High Impedance, Inputs Disconnected
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FN6254.0 September 24, 2007
ISL59452 Pin Descriptions
ISL59452 (32 LD QFN) 1 2 3 4, 6, 10, 16, 17, 22, 23, 27, 32 5, 19, 20, 28 7 8 9 11 12 13 14 15 18 21 24 25 26 PIN NAME R1 B1 G1 GND V+ R2 B2 G2 R3 B3 G3 S1 S0 GOUT BOUT ROUT AV2 HIZ EQUIVALENT CIRCUIT Circuit 1 Circuit 1 Circuit 1 Circuit 4 Circuit 4 Circuit 1 Circuit 1 Circuit 1 Circuit 1 Circuit 1 Circuit 1 Circuit 2 Circuit 2 Circuit 3 Circuit 3 Circuit 3 Circuit 2 Circuit 2 Channel 1 Red/Pr/Chroma Input Channel 1 Blue/Pb/Chroma Input Channel 1 Green/Luma Input Ground Positive Supply. Bypass to GND with 0.01F and 1nF capacitors. Channel 2 Red/Pr/Chroma Input Channel 2 Blue/Pb/Chroma Input Channel 2 Green/Luma Input Channel 3 Red/Pr/Chroma Input Channel 3 Blue/Pb/Chroma Input Channel 3 Green/Luma Input Channel selection pin MSB (binary logic code). This pin does not have internal pull-up or pull-down resistors Channel selection pin LSB (binary logic code). This pin does not have internal pull-up or pull-down resistors Green/Luma Output Blue/Pb/Chroma Output Red/Pr/Chroma Output Gain Set. Set to logic high for gain of x2 (+6dB), or set to logic low for a gain of x1 (0dB). If left floating, an internal pull-down resitor pulls this pin low (300k pull-down). Output disable (active high). Internal pull-down resistor ensures the device will be active with no connection to this pin. A logic high, puts the outputs in a high impedance state. Use this state to control logic when more than one MUX-amp share the same video output line. During high impedance state, there is a 2k pull-down present at each output. If left floating, an internal pull-down resistor pulls this pin low (300k pull-down). Channel 0 Red/Pr/Chroma Input Channel 0 Blue/Pb/Chroma Input Channel 0 Green/Luma Input Exposed Pad. Connect to GND
V+ V+ LOGIC PIN IN * OUT * V+
DESCRIPTION
29 30 31 PAD
R0 B0 G0 EP
Circuit 1 Circuit 1 Circuit 1
GND GND
CIRCUIT 2
*NOT ALWAYS PRESENT. REFER TO PIN DESCRIPTION
GND
CIRCUIT 1
CIRCUIT 3
THERMAL HEAT SINK PAD V+
CAPACITIVELY COUPLED ESD CLAMP
~1M GND SUBSTRATE
GND
CIRCUIT 4
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FN6254.0 September 24, 2007
ISL59452
ISL59452 VIN 50 or 75 x2 *CL 2.1pF RL 150 VOUT
AC Design Considerations
High speed current-feed amplifiers are sensitive to capacitance at the inverting input and output terminals. Capacitance at the output terminal increases gain peaking and overshoot. The AC response of the ISL59452 is optimized for a total output capacitance of 2.1pF with a load of 150 (Figure 32A). When PCB trace capacitance and component capacitance exceed 2pF, overshoot becomes strongly dependent on the input pulse amplitude and slew rate. Increasing levels of output capacitance reduce stability, resulting in increased overshoot and settling time. PC board trace length (LCRIT) should be kept to a minimum in order to minimize output capacitance. At 500MHz, trace lengths approaching 1" begin exhibiting transmission line behavior and may cause excessive ringing if controlled impedance traces are not used. Figure 32B shows the optimum inter-stage circuit when the total output trace length is less than the critical length of the highest signal frequency. As a general rule of thumb the trace lengths should be less than one-tenth of the wavelength of the highest frequency component in the signal. Equation 1 shows an approximate way to calculate LCRIT in meters.
c L CRIT ------------------------------------------10 x f MAX x R (EQ. 1)
*CL Includes PCB trace capacitance FIGURE 32A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD
ISL59452 VIN 50 or 75 x2
LCRIT RS
CL
CS
RL
FIGURE 32B. INTER-STAGE APPLICATION CIRCUIT
ISL59452 VIN 50,or 75 x2
LCRIT
RS 118 86.6
TEST EQUIPMENT 50
*CL 2.1pF
*CL Includes PCB trace capacitance FIGURE 32C. 150 TEST CIRCUIT WITH 50 LOAD
c = speed of light (3 x 10^8 m/s)
ISL59452 VIN 50 or 75 x2 LCRIT TEST EQUIPMENT 50/75
fMAX = maximum frequency component R = relative dielectric of board material (e.g. FR4 = 4.2) For applications where inter-stage distances are long but pulse response is not critical, capacitor CS can be added to low values of RS to form a low-pass filter to dampen pulse overshoot. This approach avoids the need for the large gain correction required by the -6dB attenuation of the back-loaded controlled impedance interconnect. Load resistor RL is still required but can be 500 or greater, resulting in a much smaller attenuation factor. For applications where pulse response is critical and where inter-stage distances exceed LCRIT, the circuit shown in Figure 32C is recommended. Resistor RS constrains the capacitance seen by the amplifier output to the trace capacitance betweeen the output pin and the resistor. Therefore, RS should be placed as close to the ISL59452 output pin as possible. For inter-stage distances much greater than LCRIT, the back-loaded circuit shown in Figure 32D should be used with controlled impedance PCB lines, with RS and RL equal to the controlled impedance.
RS
50 or 75 *CL 2.1pF
*CL Includes PCB trace capacitance FIGURE 32D. BACKLOADED TEST CIRCUIT FOR 150 VIDEO CABLE APPLICATION FIGURE 32. AC TEST CIRCUITS
AC Test Circuits
Figure 32A and 32B illustrate the optimum output load for testing AC performance at 150 loads. Figure 32C illustrates how to use the optimal 150 load for a 50 cable. Figure 32D illustrates the optimum output load for 50 and 75 cable-driving.
Application Information
General
The ISL59452 triple 4:1 video MUX features +5V single-supply operation, high bandwidth and TTL/CMOS logic compatible gain select (AV2) of x1 (0dB) or x2 (+6dB). The ISL59452 also features buffered high impedance analog inputs and excellent AC performance at output loads down to 150 for video cabledriving. The current feedback output amplifiers are stable operating into capacitive loads. 13
Control Signals
S0, S1, AV2, and HIZ are binary coded, TTL/CMOS compatible control inputs. The S0, S1 pins select the inputs. All three output amplifiers are switched simultaneously from their respective inputs. When HIZ is pulled high, it puts the outputs in a high-impedance state. For control signal rise and
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ISL59452
fall times less than 10ns, the use of termination resistors on the control lines close to the part may be necessary to prevent reflections and to minimize transients coupled to the output. See Table 1 for the S1, S0 selection states. capacitor and the device because vias adds unwanted inductance. Larger caps can be farther away. When vias are required in a layout, they should be routed as far away from the device as possible.
HIZ State
An internal pull-down resistor ensures the device will be active with no connection to the HIZ pin. The HIZ state is established within approximately 30ns (Figure 26) by placing a logic high (>2V) on the HIZ pin. If the HIZ state is selected, the output impedance is ~2000 (Figure 12). The supply current during this state is reduced to ~3mA.
The QFN Package Requires Additional PCB Layout Rules for the Thermal Pad
The thermal pad is electrically connected to GND through the high resistance IC substrate. Its primary function is to provide heat sinking for the IC. Maximum AC performance is achieved if the thermal pad is attached to a dedicated decoupled layer in a multi-layered PC board. In cases where a dedicated layer is not possible, AC performance may be reduced at upper frequencies. * The thermal pad requirements are proportional to power dissipation and ambient temperature. A dedicated layer (oftern the ground plane) eliminates the need for individual thermal pad area. When a dedicated layer is not possible, a 1"x1" pad area is sufficient for an ISL59452 dissipating 0.5W at +50C ambient. Pad area requirements should be evaluated according to the maximum ambient temperature, the maximum supply current (including worst case signals + loads), and the thermal characteristic of the PCB.
Limiting the Output Current
No output short circuit current limit exists on these parts. All applications need to limit the output current to less than 50mA. Adequate thermal heat sinking of the parts is also required.
PC Board Layout
The AC performance of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. * Use low inductance components, such as chip resistors and chip capacitors whenever possible. * Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid sharp corners; use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PCB traces longer than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. To maintain frequency performance with longer traces, use striplines. * Match channel-to-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. * All signal I/O lines should be routed over continuous ground planes (i.e. no split planes or PCB gaps under these lines). * Put the proper termination resistors in their optimum location as close to the device as possible. * When testing, use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. * Decouple well, using aminimum of 2 power supply decoupling capacitors (1000pF, 0.01F), placed as close to the devices as possible. Avoid vias between the
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 14
FN6254.0 September 24, 2007
ISL59452
Package Outline Drawing
L32.5x5
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 02/07
4X 3.5 5.00 A B 6 PIN 1 INDEX AREA 28X 0.50 6 PIN #1 INDEX AREA
25 24
32 1
5.00
3 .10 0 . 15
17
(4X) 0.15 16 9
8
0.10 M C A B 4 32X 0.23 - 0.05
+ 0.07
32X 0.40 0.10
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 0.1
C
BASE PLANE
SEATING PLANE 0.08 C
( 4. 80 TYP ) ( 3. 10 )
( 28X 0 . 5 )
SIDE VIEW
(32X 0 . 23 )
C ( 32X 0 . 60)
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
15
FN6254.0 September 24, 2007

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